PLL lock graphic example - Printable Version +- ARCHIVE: Australian Ham Radio Discussion Forum ( AHRDF ) (https://www.ahrdf.net/forum) +-- Forum: GENERAL (https://www.ahrdf.net/forum/forum-29.html) +--- Forum: General Discussion (https://www.ahrdf.net/forum/forum-9.html) +--- Thread: PLL lock graphic example (/thread-785.html) |
PLL lock graphic example - VK6RO - 02-05-2019 Vk6UU has been looking at the PLL lock times etc on a local perth repeater and a repeater maybe 180km east of Perth. Interesting to actually observe the actions of PLL lock times and stability of repeaters during and after after lock. See below the info by VK6UU posted locally. Links are for photos of the 9700 screen Not sure how exactly to insert graphics into a post... IC9700 vk6ro e&oe Perth repeater VK6RLM https://1drv.ms/u/s!AtqPG0zIQKxvgc1MAP-EqMluO_H8_A During Sunday's WARG net the turn on of VK6RLM was observed on the 9700 waterfall. What it basically shows is the PLL of the TX locking to frequency. This is probably normal for a PLL radio. Some explanation of the screen shot. When the TX first transmits it starts a bit over 2 KHz low and quickly goes to 2 KHz high before locking on 146.750. The time is less than half a second to lock. This is probably not a fault just a PLL radio locking to frequency. Kelleberrin repeater in the bush This morning VK6RKN was being heard at my QTH. Note it also has a tell tail PLL lock up signature. On key up the repeater starts 1.2 KHz low. The final transmit frequency is 200 Hz high The repeater is a Yaesu Fusion DR-1X in analogue mode only. https://1drv.ms/u/s!AtqPG0zIQKxvgc1NEOxoTDHybXlosQ RE: PLL lock graphic example - VK4ADC - 02-05-2019 Frequency drift is more likely the reference oscillator for the transmitter (and/or companion receiver if that uses the same frequency source) shifting higher as the unit's temperature rises with the power dissipation during the transmit cycle. The reference oscillator then drifts lower during every receive cycle, higher again each transmit cycle, et adfinitum. Typically such up/down drift is poor mechanical layout / design - proximity of the reference oscillator to the chassis and heatsink area. It is not a PLL lock time effect that you are describing - that manifests as a quick jump from off-frequency to on-frequency in a matter of a second or far less - if it is even visible. The frequency subsequently does not shift. |